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Model 1602P PCI Single Board Data System

Product Support

 

  • PCI-bus version of Acroamatics VME-bus Model 1502V

  • Processes PCM streams to 32 MHz

  • 32-bit instruction words

  • Non-segmented programs

  • Chapter 8 decommutation

  • Decommutates packetized TM data

  • Current value table

  • Frame buffering system

  • Programmable output formatting

  • Tandem HOTLink™ output

  • Optional plug-on modules

    Bit Synchronizer

    IRIG time translator/generator

    Format simulator

 

Program Manual

Technical Manual

Datasheet

Technical Specs

Software & Drivers

Supplemental System Products

472M Bit Sync Mezzanine

470M Time/Sim Mezz

Cabling Options

Overview

 

The Model 1602P is a stored program PCM frame synchronizer and data decommutator, capable of real-time decommutation of the most complex computer generated, high rate PCM formats, at rates to 32 MHz. The Model 1602P provides six sub-frame decommutators and two memories of 1 MB each, for instructions and data. It also allows for the addition of two mezzanine cards, the 472M PCM Bit Synchronizer module and the 470M Time Code Generator/Translator including a PAM/PCM Format Simulator. All Acroamatics documentation is supplied on CD-ROM.
 
Possible Options
 

Model 472M The 472M PCM Bit Synchronizer is a state-of-the-art Bit Synchronizer featuring tunable data rates from 8 Hz to 32 MHz for NRZ codes and 8 Hz to 10 MHz for all others.

 
Model 470M The 470M Time Code Generator/Translator + PAM/PCM Format Simulator combines time code translation and generation and format simulation on a single plug-on mezzanine module. Generates and translates IRIG A, B, and G time codes. Generates all IRIG standard and randomized PCM codes. Generates complex formats with dynamic data and sub-frames.

 

System Software

 

GUI Setup and Operation Status for the 1602P is controlled via a single interface with drop down menus.

Technical Specs

 

FUNCTION

Sources

Program selectable, one of four inputs: three NRZ-L

Data and 0º Clock inputs; one internal Test Pattern input.

Impedance

50 Ohm input impedance, TTL compatible.

Bit Rate

Up to 32M bits per second.

Polarity

Programmable, automatic polarity correction.

Word Length

Programmable, 1 to 32 bit word length for each input.

Word Orientation

Programmable, MSB/LSB orientation for each input word.

 

Parity

Selectable leading, trailing, or no parity checking for each word.

SYNCHRONIZATION

Mainframe Sync

Mainframe synchronization provides for programmable synch pattern and mask, complement pattern recognition, and variable length frame decommutation. The pattern may be up to 64 bits in length.

Subframe Sync

Six independent synchronizers are capable of decommutating sub-frames within subframes. Subframes synchronize to fixed recycle patterns, complement frame sync patterns, and various ID patterns. Both recycle and ID patterns may be assembled from multiple word locations. Recycle patterns may be up to 32 bits long.

ID Sync

Two types of ID synchronization are supported: JAM patterns of arbitrary values, and incrementing or decrementing frame counters with limit checking.

ID sync words may be up to 16 bits in length.

Sync Strategy

Programmable Search-Check-Lock sync strategy, bit error tolerance,and bit slip window provide reliable frame synchronization.

Asynchronous Formats

Subframe synchronizer may be programmed to decommutate embedded formats having unique frame sync patterns and format structures.

Format Switching

 16 testable flags store the results of bit or word comparisons on the input stream to control decommutation.

OUTPUT

Data

Data is available to the host computers as memory-mapped frame buffers or CVT or as a data stream selectably transferred by PCI bus DMA or HOTLink™.

Data is 32 bits with programmable MSB/LSB output word justification, sign extension or zero insertion for LSB output.

ID Tag

Unique ID tags may be assigned to each word: a total of 131,072 tags is possible. The 32-bit ID word includes ID tag, status, and microsecond time.

Frame Quality

Frame quality word is generated containing bit sync and frame sync status for downstream data

validation.

2 Serial PCM Outputs

Two programmably controlled RS-422 compatible

serial output channels are available.

PHYSICAL

Format

Standard PCI: Full length single slot

Cooling Requirements

30 Linear FPM

Power Requirements

+3.3VDC @ 1.5A, +5VDC @ 1.0A, ±12VDC if 472M attached

Dimensions

4.20" (10.67cm) H x 12.5" (31.75cm) W x .55" (1.4cm) D

Temperature

Operating 0 to +40°C, non-operating –40 to +86°C

Relative Humidity

Up to 90% non-condensing

Shock

Operating 6G, Non-operating 25G

Vibration

Operating .3G, 5 to 2000 Hz, Non-operating .8G, 5 to 500 Hz

specifications subject to change without notice

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