Input Bus
The Distribution System interfaces eight possible PCM frame synchronizers,
an IRIG time port, and an analog-to-digital port. Two 32-bit words are
multiplexed onto the bus and are queued to the Distribution System. The
first word is the identifier that contains fine time, status, stream
identification, and ID tag. The second word contains the data. The
Distribution System supports up to 128k unique ID tags.
Distribution System
The Distribution System contains up to 256k 32-bit words of high
speed static RAM. The ID tag accompanying each data sample addresses the
lower 128k block of memory. The content of the word addressed by the tag
is called the vector and points to the start of the processing table
located in the upper 64k (256k optional) of memory.
The processing table specifies the data stream processor, the algorithm to
be performed, parameters required to process the raw input, and the final
destination. The ID, data, and processing instructions are transmitted to
four possible data stream processors across the bi-directional, 32-bit
Distribution Bus.
Device Bus
Each stream processor performs a comprehensive set of algorithms for
processing both floating point and integer data. The results of this
processing are placed on the Device Bus. The Device Bus interfaces output
devices such as: digital-to-analog outputs, digital discrete outputs, a
feedback port to the Distribution input, and a VME Host DMA channel. The
Device Bus supports up to eight output devices.
Host Interface
The Host Interface provides controls for single stepping and running the
Distribution System and 505V Programmable Data Stream Processors, as well
as outputting and receiving data on the Device Bus. The Host DMA channel
provides a data path where processed data may be routed to memory and
networking devices residing on the VME bus. The DMA circuitry includes bus
master logic that supports continuous transfers of up to 64K 32-bit words.
