Model 520V VME Analog Synchronizer

The Model 520V Analog Synchronizer will decommutate PAM and PDM data at rates from 10 to 250,000 channels per second. The output of the Model 520V Analog Synchronizer is either serial PCM or parallel ID tagged data for direct processing. The Model 520V takes

advantage of advances in both analog and digital circuitry to provide a decommutator which digitally processes many previously analog functions. The 520V uses a 16-bit microcomputer to control PAM/PDM decommutation. The processor serves as the overall system operations manager. The processor interprets decommutator setup and control information from either an RS232 channel, available on P2 pins, or from the host computer via the VME bus. The processor also controls auto-ranging and input signal conditioning. The auto-range feature provides automatic, adjustment-free correction of the input amplitude and offset for immediate channel and frame synchronization. After achieving synchronization, the processor monitors the 0% and 100% reference channels and changes the gain & offset to maintain the data accuracy of the incoming stream. During data acquisition the processor also corrects for deviations in the input rate. All Acroamatics documentation is supplied on CD-ROM.

System Software

GUI Setup and Operation Status for the 520V is controlled via a single interface with drop down menus.

Technical Specs

INPUT
Sources	Program selectable, One of two inputs
Impedance	10kΩ input impedance, single ended
Channel Rate	250k channels for NRZ, 125k channels for RZ, and 10k channels for PDM
Polarity	Normal or inverted
Frame Length	Up to 999 channels per frame
Input Adjustments	Microprocessor controlled automatic input ranging normalizes the input within two frames, allowing adjustment-free operation with input signals of 1 to 20 Volts peak to peak. Programmable auto set delay holds input values for up to 64 seconds when sync is lost
SYNCHRONIZATION
PAM NRZ	Programmable pattern and tolerance for 3 to 5 consecutive channels, user selectable
PAM RZ	One missing channel
PDM	One channel missing high or one missing low
SYNC STRATEGY	Programmable sync strategy allows user to specify transitions from Search to Check to Lock and back
OUTPUT
Data	12 bit offset binary or 2’s complement value can be right or left-justified in the parallel output word. TTL compatible voltage levels
ID Tag	17 bit ID tag, TTL compatible voltage levels
Guard Bands	Programmable guard bands allow overscale data to be output as meaningful values
DAC Output	Selected channel output as ±1.25 Volt analog signal
Serial PCM Outputs	10 bit programmable sync pattern, data and 0° clock
PHYSICAL
Format	Single Slot 6U VME
Cooling Requirements	30 Linear FPM
Power Requirements	+5VDC at 2 Amps, +12VDC at 1 Amp, -12VDC at 50 mA
Temperature	Operating 0 to +40°C, non-operating –40 to +86°C
Relative Humidity	Up to 90% non-condensing
Shock	Operating 6G, Non-operating 50G
Vibration	Operating 0.5G, 5 to 2000Hz, Non-Operating 1.2G, 5 to 500Hz
specifications subject to change without notice